A sub-1 V bootstrap pass-transistor logic

IEICE Transactions on Electronics

Volumn E86-C, Issue 4, 2003, Pages 604-611

  Fujii, Koji ^a   Douseki, Takakuni ^a  

^a NTT CORPORATION   (Japan)

Author keywords

Adder; Bootstrap; Low voltage; Pass transistor logic

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; ELECTRIC CURRENT CONTROL; ELECTRIC POWER SUPPLIES TO APPARATUS; SHORT CIRCUIT CURRENTS; TIMING CIRCUITS; TRANSISTORS; VOLTAGE CONTROL;

ARITHMETIC LOGIC UNIT; BOOTSTRAP PASS TRANSISTOR LOGIC; SYNCHRONOUS TIMING SEQUENCE;

LOGIC CIRCUITS;

EID: 0142155095     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (9)

1. T. Douseki, S. Shigematsu, J. Yamada, M. Harada, H. Inokawa, and T. Tsuchiya, "0.5 V SIMOX-MTCMOS circuit with 200-ps logic gate," ISSCC Dig. of Tech. Papers, pp.84-85, Feb. 1996.
2. K. Yano, Y. Sasaki, K. Rikino, and K. Seki, "Top-down pass-transistor logic design," IEEE J. Solid-State Circuits, vol.31, no.6, pp.792-803, June 1996.
3. F. Assaderaghi, D. Sinitsky, S. Parke, J. Bokor, P.K. Ko, and C. Hu, "A dynamic threshold voltage MOSFET(DTMOS) for ultra-low voltage operation," IEEE IEDM Tech. Dig., pp.809-812, 1994.
4. T. Fuse, Y. Oowaki, M. Terauchi, S. Watanabe, M. Yoshimi, K. Ohuchi, and J. Matsunaga, "0.5 V SOI CMOS pass-gate logic," ISSCC Dig. of Tech. Papers, pp.88-89, Feb. 1996.
5. J.M. Rabaey, Digital Integrated Circuits, p.217, Prentice-Hall, 1996.
6. J. Koomen and J. van den Akker, "A MOST inverter with improved switching speed," IEEE J. Solid-State Circuits, vol.7, no.3, pp.231-236, June 1972.
7. C. Seitz, A. Frey, S. Mattisson, S. Rabin, D. Speck, and J.L.A. van de Snepscheut, "Hot-clock nMOS," Proc. 1985 Chapel Hill Conf. on VLSI, p.1, 1985.
8. K. Fujii, T. Douseki, and M. Harada, "Sub-1 V triple-threshold CMOS/SIMOX circuit for active power reduction," ISSCC Dig. of Tech. Papers, pp.190-191, Feb. 1998.
9. R.H. Crawford, MOSFET in Circuit Design, chs. 4, pp.73-82, McGraw-Hill, New York, 1967.