On test pattern compaction using random pattern fault simulation

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1998, Pages 464-469

  Kajihara, Seiji ^a   Saluja, Kewal ^a  

^a KYUSHU INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; RANDOM PROCESSES; VECTORS;

RANDOM PATTERN FAULT SIMULATION; TEST PATTERN COMPACTION;

INTEGRATED CIRCUIT TESTING;

EID: 0031680073     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)