-
1
-
-
0027347715
-
Lazy caching
-
Y. Afek, G. Brown, and M. Merritt, "Lazy Caching," ACM Trans Programming Languages and Systems, vol. 15, no. 1, pp. 182-205, 1993.
-
(1993)
ACM Trans Programming Languages and Systems
, vol.15
, Issue.1
, pp. 182-205
-
-
Afek, Y.1
Brown, G.2
Merritt, M.3
-
2
-
-
0029722268
-
Model-checking of correctness conditions for concurrent objects
-
R. Alur, K.L. McMillan, and D. Peled, "Model-Checking of Correctness Conditions for Concurrent Objects," Proc. 11th Ann. IEEE Symp. Logic in Computer Science, pp. 219-228, 1996.
-
(1996)
Proc. 11th Ann. IEEE Symp. Logic in Computer Science
, pp. 219-228
-
-
Alur, R.1
McMillan, K.L.2
Peled, D.3
-
3
-
-
84958779573
-
Using timestamping and history variables to verify sequential consistency
-
G. Berry, H. Comon, and A. Finkel, eds.
-
T. Arons, "Using Timestamping and History Variables to Verify Sequential Consistency," Proc. CAV 01: Computer-Aided Verification Conf., G. Berry, H. Comon, and A. Finkel, eds., pp. 423-435, 2001.
-
(2001)
Proc. CAV 01: Computer-Aided Verification Conf.
, pp. 423-435
-
-
Arons, T.1
-
4
-
-
0032647513
-
Multicast snooping: A new coherence method using a multicast address network
-
E. Bilir, R. Dickson, Y. Hu, M. Plakal, D. Sorin, M. Hill, and D. Wood, "Multicast Snooping: A New Coherence Method Using a Multicast Address Network," Proc. 26th Ann. Int'l Symp. Computer Architecture, 1999.
-
Proc. 26th Ann. Int'l Symp. Computer Architecture, 1999
-
-
Bilir, E.1
Dickson, R.2
Hu, Y.3
Plakal, M.4
Sorin, D.5
Hill, M.6
Wood, D.7
-
5
-
-
0033722744
-
Piranha: A scalable architecture based on sigle-chip multiprocessing
-
L.A. Barroso, K. Gharachorloo, R. McNamara, A. Nowatzyk, S. Qadeer, B. Sano, S. Smith, R. Stets, and B. Verghese, "Piranha: A Scalable Architecture Based on Sigle-Chip Multiprocessing," Proc. 27st Ann. Int'l Symp. Computer Architecture, pp. 282-293, 2000.
-
(2000)
Proc. 27st Ann. Int'l Symp. Computer Architecture
, pp. 282-293
-
-
Barroso, L.A.1
Gharachorloo, K.2
McNamara, R.3
Nowatzyk, A.4
Qadeer, S.5
Sano, B.6
Smith, S.7
Stets, R.8
Verghese, B.9
-
6
-
-
0002367651
-
Design and synthesis of synchronization skeletons using branching-time temporal logic
-
E.M. Clarke and E.A. Emerson, "Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic," Proc. Workshop Logic of Programs, pp. 52-71, 1981.
-
(1981)
Proc. Workshop Logic of Programs
, pp. 52-71
-
-
Clarke, E.M.1
Emerson, E.A.2
-
7
-
-
0027734857
-
Verification of the futurebus+ cache coherence protocol
-
E.M. Clarke, O. Grumberg, H. Hiraishi, S. Jha, D.E. Long, K.I. McMillan, and L.A. Ness, "Verification of the Futurebus+ Cache Coherence Protocol," Proc. 11th IFIP WG10.2 Int'l Conf. Computer Hardware Description Languages and their Applications, pp. 15-30, 1993.
-
(1993)
Proc. 11th IFIP WG10.2 Int'l Conf. Computer Hardware Description Languages and Their Applications
, pp. 15-30
-
-
Clarke, E.M.1
Grumberg, O.2
Hiraishi, H.3
Jha, S.4
Long, D.E.5
McMillan, K.I.6
Ness, L.A.7
-
9
-
-
0003691648
-
-
Alpha Architecture Committee; Digital Press
-
Alpha Architecture Committee, Alpha Architecture Reference Manual. Digital Press, 1998.
-
(1998)
Alpha Architecture Reference Manual
-
-
-
10
-
-
84944400032
-
Automatic verification of parameterized cache coherence protocols
-
E.A. Emerson and A.P. Sistla, eds.
-
G. Delzanno, "Automatic Verification of Parameterized Cache Coherence Protocols," CAV 2000: Computer Aided Verification, E.A. Emerson and A.P. Sistla, eds., pp. 53-68, 2000.
-
(2000)
CAV 2000: Computer Aided Verification
, pp. 53-68
-
-
Delzanno, G.1
-
11
-
-
84947927151
-
Using formal verification/analysis methods on the critical path in system design: A case study
-
P. Wolper, ed.
-
Á.Th. Eíriksson and K.L. McMillan, "Using Formal Verification / Analysis Methods on the Critical Path in System Design: A Case Study," Proc. Computer Aided Verification Conf., P. Wolper, ed., pp. 367-380, 1995.
-
(1995)
Proc. Computer Aided Verification Conf.
, pp. 367-380
-
-
Eíriksson, Á.Th.1
McMillan, K.L.2
-
12
-
-
0031211417
-
Testing shared memories
-
P.B. Gibbons and E. Korach, "Testing Shared Memories," SIAM J. Computing, vol. 26, no. 4, pp. 1208-1244, 1997.
-
(1997)
SIAM J. Computing
, vol.26
, Issue.4
, pp. 1208-1244
-
-
Gibbons, P.B.1
Korach, E.2
-
13
-
-
84944030696
-
Extending memory consistency of finite prefixes to infinite computations
-
K.G. Larsen and M. Nielsen, eds.
-
M. Glusman and S. Katz, "Extending Memory Consistency of Finite Prefixes to Infinite Computations," Proc. CONCUR 01 Conf.: Theories of Concurrency, K.G. Larsen and M. Nielsen, eds., pp. 411-425, 2001.
-
(2001)
Proc. CONCUR 01 Conf.: Theories of Concurrency
, pp. 411-425
-
-
Glusman, M.1
Katz, S.2
-
14
-
-
84957061332
-
Verifying sequential consistency on shared-memory multiprocessor systems
-
N. Halbwachs and D. Peled, eds.
-
T.A. Henzinger, S. Qadeer, and S.K. Rajamani, "Verifying Sequential Consistency on Shared-Memory Multiprocessor Systems," Proc. CAV '99 Conf.: Computer Aided Verification. N. Halbwachs and D. Peled, eds., pp. 301-315, 1999.
-
(1999)
Proc. CAV '99 Conf.: Computer Aided Verification
, pp. 301-315
-
-
Henzinger, T.A.1
Qadeer, S.2
Rajamani, S.K.3
-
15
-
-
0030211668
-
Better verification through symmetry
-
C.N. Ip and D.L. Dill, "Better Verification through Symmetry," Formal Methods in System Design, vol. 9, nos. 1-2, pp. 41-75, 1996.
-
(1996)
Formal Methods in System Design
, vol.9
, Issue.1-2
, pp. 41-75
-
-
Ip, C.N.1
Dill, D.L.2
-
16
-
-
0028343484
-
The Stanford FLASH multiprocessor
-
J. Kuskin, D. Ofelt, M. Heinrich, J. Heinlein, R. Simoni, K. Gharachorloo, J. Chapin, D. Nakahira, J. Baxter, M. Horowitz, A. Gupta, M. Rosenblum, and J. Hennessy, "The Stanford FLASH Multiprocessor," Proc. 21st Ann. Int'l Symp. Computer Architecture. pp. 302-313, 1994.
-
(1994)
Proc. 21st Ann. Int'l Symp. Computer Architecture
, pp. 302-313
-
-
Kuskin, J.1
Ofelt, D.2
Heinrich, M.3
Heinlein, J.4
Simoni, R.5
Gharachorloo, K.6
Chapin, J.7
Nakahira, D.8
Baxter, J.9
Horowitz, M.10
Gupta, A.11
Rosenblum, M.12
Hennessy, J.13
-
17
-
-
0001123063
-
Verification of distributed programs using representative interleaving sequences
-
S. Katz and D. Peled, "Verification of Distributed Programs Using Representative Interleaving Sequences," Distributed Computing, vol. 6, no. 2, pp. 107-120, 1992.
-
(1992)
Distributed Computing
, vol.6
, Issue.2
, pp. 107-120
-
-
Katz, S.1
Peled, D.2
-
18
-
-
0017996760
-
Time, clocks, and the ordering of events in a distributed program
-
L. Lamport, "Time, Clocks, and the Ordering of Events in a Distributed Program," Comm. ACM, vol. 21, no. 7, pp. 558-565, 1978.
-
(1978)
Comm. ACM
, vol.21
, Issue.7
, pp. 558-565
-
-
Lamport, L.1
-
19
-
-
0018518477
-
How to make a multiprocessor computer that correctly executes multiprocess programs
-
L. Lamport, "How to Make a Multiprocessor Computer that Correctly Executes Multiprocess Programs," IEEE Trans. Computers, vol. 28, no. 9, pp. 690-691, 1979.
-
(1979)
IEEE Trans. Computers
, vol.28
, Issue.9
, pp. 690-691
-
-
Lamport, L.1
-
20
-
-
0028424892
-
The temporal logic of actions
-
L. Lamport, "The Temporal Logic of Actions," ACM Trans. Programming Languages and Systems, vol. 16, no. 3, pp. 872-923, 1994.
-
(1994)
ACM Trans. Programming Languages and Systems
, vol.16
, Issue.3
, pp. 872-923
-
-
Lamport, L.1
-
21
-
-
0141731008
-
Verification of a multiprocessor cache protocol using simulation relations and higher-order logic
-
P. Loewenstein and D.L. Dill, "Verification of a Multiprocessor Cache Protocol Using Simulation Relations and Higher-Order Logic," Formal Methods in System Design, vol. 1, no. 4, pp. 355-383, 1992.
-
(1992)
Formal Methods in System Design
, vol.1
, Issue.4
, pp. 355-383
-
-
Loewenstein, P.1
Dill, D.L.2
-
22
-
-
0025429467
-
The directory-based cache coherence protocol for the DASH multiprocessor
-
D. Lenoski, J. Laudon, K. Gharachorloo, A. Gupta, and J. Hennessy, "The Directory-Based Cache Coherence Protocol for the DASH Multiprocessor," Proc. 17th Ann. Int'l Symp. Computer Architecture, pp. 148-159, 1990.
-
(1990)
Proc. 17th Ann. Int'l Symp. Computer Architecture
, pp. 148-159
-
-
Lenoski, D.1
Laudon, J.2
Gharachorloo, K.3
Gupta, A.4
Hennessy, J.5
-
23
-
-
0033338240
-
Lazy caching in TLA
-
P. Ladkin, L. Lamport, B. Olivier, and D. Roegel, "Lazy Caching in TLA," Distributed Computing, vol. 12, nos. 2/3, pp. 151-174, 1999.
-
(1999)
Distributed Computing
, vol.12
, Issue.2-3
, pp. 151-174
-
-
Ladkin, P.1
Lamport, L.2
Olivier, B.3
Roegel, D.4
-
26
-
-
0008879028
-
Formal design and verification methods for shared memory systems
-
PhD thesis, Univ. of Utah
-
R.P. Nalumasu, "Formal Design and Verification Methods for Shared Memory Systems," PhD thesis, Univ. of Utah, 1999.
-
(1999)
-
-
Nalumasu, R.P.1
-
27
-
-
84863901125
-
The 'test model-checking' approach to the verification of formal memory models of multiprocessors
-
A.J. Hu and M.Y. Vardi, eds.
-
R.P. Nalumasu, R. Ghughal, A. Mokkedem, and G. Gopalakrishnan, "The 'Test Model-Checking' Approach to the Verification of Formal Memory Models of Multiprocessors," Proc. Conf. Computer Aided Verification, A.J. Hu and M.Y. Vardi, eds., pp. 464-476, 1998.
-
(1998)
Proc. Conf. Computer Aided Verification
, pp. 464-476
-
-
Nalumasu, R.P.1
Ghughal, R.2
Mokkedem, A.3
Gopalakrishnan, G.4
-
28
-
-
84944677742
-
PVS: A prototype verification system
-
D. Kapur, ed.
-
S. Owre, J.M. Rushby, and N. Shankar, "PVS: A Prototype Verification System," Proc. CADE 92: 11th Int'l Conf. Automated Deduction, D. Kapur, ed., pp. 748-752, 1992.
-
(1992)
Proc. CADE 92: 11th Int'l Conf. Automated Deduction
, pp. 748-752
-
-
Owre, S.1
Rushby, J.M.2
Shankar, N.3
-
29
-
-
0029352644
-
A new approach for the verification of cache coherence protocols
-
F. Pong and M. Dubois, "A New Approach for the Verification of Cache Coherence Protocols," IEEE Trans. Parallel and Distributed Systems, vol. 6, no. 8, pp. 773-787, 1995.
-
(1995)
IEEE Trans. Parallel and Distributed Systems
, vol.6
, Issue.8
, pp. 773-787
-
-
Pong, F.1
Dubois, M.2
-
30
-
-
84957377771
-
Protocol verification by aggregation of distributed transactions
-
R. Alur and T.A. Henzinger, eds.
-
S. Park and D.L. Dill, "Protocol Verification by Aggregation of Distributed Transactions," Proc. CAV 96 Conf.: Computer Aided Verification, R. Alur and T.A. Henzinger, eds., pp. 300-310, 1996.
-
(1996)
Proc. CAV 96 Conf.: Computer Aided Verification
, pp. 300-310
-
-
Park, S.1
Dill, D.L.2
-
31
-
-
0031630017
-
Lamport clocks: Verifying a directory cache-coherence protocol
-
M. Plakal, D.J. Sorin, A.E. Condon, and M.D. Hill, "Lamport Clocks: Verifying a Directory Cache-Coherence Protocol," Proc. 10th Ann. ACM Symp. Parallel Algorithms and Architectures, pp. 67-76, 1998.
-
(1998)
Proc. 10th Ann. ACM Symp. Parallel Algorithms and Architectures
, pp. 67-76
-
-
Plakal, M.1
Sorin, D.J.2
Condon, A.E.3
Hill, M.D.4
-
32
-
-
0001439560
-
Specification and verification of concurrent systems in CESAR
-
M. Dezani-Ciancaglini and U. Montanari, eds.
-
J. Queille and J. Sifakis, "Specification and Verification of Concurrent Systems in CESAR," Proc. Fifth Int'l Symp. Programming, M. Dezani-Ciancaglini and U. Montanari, eds., pp. 337-351, 1981.
-
(1981)
Proc. Fifth Int'l Symp. Programming
, pp. 337-351
-
-
Queille, J.1
Sifakis, J.2
-
33
-
-
0141731015
-
-
D.L. Weaver and T. Germond, eds. Prentice Hall
-
The SPARC Architecture Manual, D.L. Weaver and T. Germond, eds. Prentice Hall, 1999.
-
(1999)
The SPARC Architecture Manual
-
-
-
34
-
-
85051051500
-
Expressing interesting properties of programs in propositional temporal logic
-
P. Wolper, "Expressing Interesting Properties of Programs in Propositional Temporal Logic," Proc. 13th Ann. Symp. Principles of Programming Languages, pp. 184-193, 1986.
-
(1986)
Proc. 13th Ann. Symp. Principles of Programming Languages
, pp. 184-193
-
-
Wolper, P.1
-
35
-
-
84958641324
-
Model checking TLA+ Specifications
-
Y. Yu, P. Manolios, and L. Lamport, "Model Checking TLA+ Specifications," Proc. CHARME 99: IFIP Working Conf. Correct Hardware Design and Verification Methods, pp. 54-66, 1999.
-
(1999)
Proc. CHARME 99: IFIP Working Conf. Correct Hardware Design and Verification Methods
, pp. 54-66
-
-
Yu, Y.1
Manolios, P.2
Lamport, L.3
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