High fan-in circuit design

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 1, 1996, Pages 91-96

  Clark, Lawrence T ^a,b,c,d,e,f   Taylor, Gregory F ^a,b,g,h,i  

^a IEEE

^b INTEL CORPORATION   (United States)

^c NORTHERN ARIZONA UNIVERSITY   (United States)

^d ARIZONA STATE UNIVERSITY   (United States)

^e ASU

^f VLSI Technology   (Spain)

^g RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^h Bipolar Integrated Technology

ⁱ Rensselaer Polytechnic Institute ^*

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; BIPOLAR TRANSISTORS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ELECTRONS; LEAKAGE CURRENTS; LOGIC CIRCUITS; MOS DEVICES; SEMICONDUCTOR JUNCTIONS;

BIPOLAR JUNCTION TRANSISTOR; DRAIN CAPACITANCE; DYNAMIC CIRCUITS; PARASITIC CAPACITANCE;

LOGIC DESIGN;

EID: 0029778506     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.485870     Document Type: Article

References (9)

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3. S. Joshi et al., "Poly emitter bipolar hot carrier effects in an advanced BiCMOS technology," in Proc. IEDM, 1987, pp. 182-185.
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5. A. Alverez, BiCMOS Technology and Applications. Boston, MA: Kluwer, 1989.
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7. eff < 0.4 microns," in BCTM Proc., 1993, pp. 184-187.
8. B. Krick et al., "A 150 MHz 0.6 μm BiCMOS superscalar microprocessor," IEEE J. Solid-State Circuits, vol. 29, no. 12, pp. 1455-1463, Dec. 1994.
9. M. Bohr et al., "A high performance 0.35 μm logic technology for 3.3 and 2.5 V operation," in Proc. IEDM, 1995, pp. 241-244.