Optimization of align marks and overlay targets in VIA first dual damascene process

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5038 I, Issue , 2003, Pages 415-427

  Shin, Dae Ung ^a   Jeong, Young Bae ^a   Park, Jeong Lyeol ^a   Choi, Jae Sung ^a   Lee, Jeong Gun ^a   Lee, Dai Hoon ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

Alignment; Dual damascene; Image contrast; Overlay

Indexed keywords

ANTIREFLECTION COATINGS; COPPER; DIELECTRIC MATERIALS; HELIUM NEON LASERS; OPTICAL SENSORS; OPTIMIZATION; PHOTORESISTS;

ALIGNMENT MARKS; BOTTOM ANTI REFLECTION COATING PROCESSING; DUAL DAMASCENE PROCESS; IMAGE CONTRAST; MULTILEVEL COPPER INTERCONNECTION; OVERLAY MEASUREMENT; OVERLAY TARGETS;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0141612001     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.485032     Document Type: Conference Paper

References (5)

1. Scott Warrick, "Integration of New Alignment Designs in Dual Inlaid Copper Interconnect Processes", Proc. SPIE, vol.4691, 2002, pp.971-980
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3. Quiang Wu, "Ultra-fast Wafer Alignment Simulation Based on Thin Film Theory", Proc. SPIE, vol.4689, 2002, pp.364-373
4. Beth Russo, "Overlay Tool Comparison for sub-130nm Technologies", Proc. SPIE, vol.4689, 2002, pp.261-272
5. Vincent Vachellerie, "Overlay Metrology Results on Leading Edge Cu Processes", Proc. SPIE, vol.4689, 2002, pp.223-236