Overlay tool comparison for sub-130 nm technologies

Proceedings of SPIE-The International Society for Optical Engineering

Volumn 4689 I, Issue , 2002, Pages 261-272

  Russo, Beth ^a,b   Bishop, Michael ^a   Benoit, Dave ^b   Silver, Richard ^c  

^a SEMATECH   (United States)

^b MOTOROLA INC   (United States)

^c NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FITS AND TOLERANCES; LIGHT SOURCES; MASKS; PROCESS CONTROL;

OVERLAY METROLOGY;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0036028774     PISSN: 0277786X     EISSN: None     Source Type: Journal    
DOI: 10.1117/12.473464     Document Type: Article

References (6)

1. Benoit, D., et al. 2000. Overlay Metrology Equipment Specification for Sub-180nm Device Technology, Version 1.0: November 2000.
2. Wolf, S. and Tauber, R.N. Silicon Processing for the VLSI Era, Vol. 1, pp. 473-474. Lattice Press, California, 1986.
3. International Technology Roadmap for Semiconductors: 2001 Edition, Semiconductor Industry Association.
4. Mack, C. Introduction to Optical Lithography. Book 2, p. 85. FINLE Technologies, 1997.
5. Diebold, Alain C. Handbook of Silicon Semiconductor Metrology, pp. 414-415. Marcel Decker, New York, 2001.
6. Guide for Measurement System Capability Analysis (SEMI E89-0999), Semiconductor Equipment and Materials International.