Simplified current and delay models for deep submicron CMOS digital circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Mansour, Makram M ^a   Shanbhag, Naresh R ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CURRENT MEASUREMENT; MATHEMATICAL MODELS;

DELAY ESTIMATION; DRAIN CURRENT ESTIMATES;

INTEGRATED CIRCUIT LAYOUT;

EID: 0036294973     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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2. Modeling and simulation of insulated-gate field-effect transistor switching circuits
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5. A physical α-power law MOSFET model
6. A comprehensive delay macro modeling for submicrometer CMOS logics
7. An analytical CMOS inverter delay model including channel-length modulations
8. Analytical model for switching transitions of submicron CMOS logics
9. CMOS inverter delay and other formulas using alpha-power law MOS model
10. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's