A Memory Using One-transistor Gain Cell on SOI(FBC) with Performance Suitable for Embedded DRAM's

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2003, Pages 93-96

  Ohsawa, Takashi ^a   Higashi, Tomoki ^a   Fujita, Katsuyuki ^a   Ikehashi, Tamio ^a   Kajiyama, Takeshi ^a   Fukuzumi, Yoshiaki ^a   Shino, Tomoaki ^a   Yamada, Hiroaki ^a   Nakajima, Hiroomi ^a   Minami, Yoshihiro ^a   Yamada, Takashi ^a   Inoh, Kazumi ^a   Hamamoto, Takeshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CHARGE; STORAGE ALLOCATION (COMPUTER); THRESHOLD VOLTAGE; TRANSISTORS;

MEMORY CHIPS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0141426756     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. S. Okhonin, M. Nagoga, J. M.Sallese and P. Fazan, "A SOI capacitor-less 1T-DRAM concept, "IEEE Int. SOI. Conf., pp. 153-154, October 2001
2. T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao and K. Sunouchi, "Memory design using one-transistor gain cell on SOI, "ISSCC Dig. Tech. Papers, pp. 152-153, February 2002
3. C. Kuo, T-J. King, C. Hu, "A capacitorless double-gate DRAM cell, "IEEE Electron Device Letters, Vol.23, No.6, pp.345-347, June 2002
4. T. Ohsawa, K. Fujita, T. Higashi, Y. Iwata, T. Kajiyama, Y. Asao and K. Sunouchi, "Memory design using a one-transistor gain cell on SOI, "IEEE J. Solid-State Circuits, Vol.37, No.11, pp.1510-1522, November 2002