Minimal energy fixed-priority scheduling for variable voltage processors

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 8, 2003, Pages 1062-1071

  Quan, Gang ^a   Hu, Xiaobo Sharon ^b  

^a University of South Carolina   (United States)

^b University of Notre Dame   (United States)

Author keywords

Dynamic voltage scaling; Fixed priority; Low power; Real time systems; Scheduling

Indexed keywords

ALGORITHMS; COST EFFECTIVENESS; ELECTRIC POWER SUPPLIES TO APPARATUS; OPTIMIZATION; REAL TIME SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SCHEDULING; VOLTAGE CONTROL;

VARIABLE VOLTAGE PROCESSORS;

MICROPROCESSOR CHIPS;

EID: 0042593198     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.814948     Document Type: Conference Paper

References (36)

1. G. Micheli and L. Benini, "System-level low power optimization: Techniques and tools," Trans. Design Auto. Elect. Syst., vol. 5, no. 2, Apr. 2000.
2. M. Pedram, "Power minimization in IC design: Principles and applications," ACM Trans. Design Auto. Elect, Syst., vol. 1, no. 1, pp. 3-56, Jan. 1996.
3. F. Najm, "A survey of power estimation techniques in VLSI circuits," IEEE Trans. VLSI Syst., vol. 2, pp. 446-455, Dec. 1994.
4. S. Devades and S. Malik, "A survey of optimization techniques targeting low power VLSI circuits," in Proc. Design Automation Conf. (DAC), 1995, pp. 242-247.
5. T. D. Burd and R. W. Brodersen, "Design issues for dynamic voltage scaling," in Proc. Int. Symp. Low Power Electronics Design (ISLPED), 2000. pp. 9-14.
6. T. Burd, "Energy-Efficient Processor System Design," Ph.D. dissertation, Dept. Elec. Eng. Comput. Sci., Univ. California, Berkeley, CA, 2001.
7. Intel, (2002) Developer manual: Intel 80 200 Processor based on Intel Xscale microarchitecture. [Online]. Available: http://developer.intel.com/design/iio/manuals/273411.htm
8. D. Laird. (2000) Crusoe Processor products and technology. [Online]. Available: http://www.transmeta.com/technology/architecture/index.html
9. AMD. (2001) Mobile and Duron Processor [Online]. Available: http://www.amd.com/
10. L. Benini, A. Bogliolo, and G. Micheli, "A survey of design techniques for system-level dynamic power management," IEEE Trans. VLSI Syst., vol. 8, pp. 299-316, June 2000.
11. J. Rabaey and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer, 1996.
12. L. Benini, A. Bogliolo, G. Paleologo, and G. Micheli, "Policy optimization for dynamic power management," IEEE Trans. Computer-Aided Design, vol. 18, pp. 813-833, June 1999.
13. Y. Lu, E. Chung, T. Simunić, L. Benini, and G. D. Micheli, "Quantitative comparison of power management algorithms," in Proc. Design Automation Test Eur. Conf. (DATE), 2000, pp. 20-26.
14. D. Ramanathan and R. Gupta, "System level online power management algorithms," in Proc. Design Automation Test Europe Conf. (DATE), 2000, pp. 606-611.
15. E. Chung, L. Benini, and G. Micheli, "Dynamic power management using adaptive learning tree," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1999, pp. 274-279.
16. Q. Qiu, Q. Wu, and M. Pedram, "Dynamic power management of complex system using generalized stochastic petri nets," in Proc. Design Automation Conf. (DAC), 2000, pp. 352-356.
17. E. Chung, L. Benini, A. Bogliolo, and G. Micheli, "Dynamic power management for nonstationary service requests," in Proc. Design Automation Test Europe Conf. (DATE), 1999, pp. 77-81.
18. I. Hong, M. Potkonjak, and M. B. Srivastava, "On-line scheduling of hard real-time tasks on variable voltage processor," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1998, pp. 653-656.
19. Y. Shin and K. Choi, "Power conscious fixed priority scheduling for hard real-time systems," in Proc. Design Automation Conf. (DAC), 1999, pp. 134-139.
20. Y. Shin, K. Choi, and T. Sakurai, "Power optimization of real-time embedded systems on variable speed processors," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 2000, pp. 365-368.
21. R. Golding, P. Bosch, and J. Wilkes, "Idleness is not sloth," in Proc. Winter USENIX Technical Conf., 1995, pp. 201-212.
22. M. Srivastava, A. Chandrakasan, and R. Brodersen, "Predictive system shutdown and other architectural techniques for energy efficient programable computation," IEEE Trans. VLSI Syst., vol. 4, no. 27, pp. 42-55, Mar. 1996.
23. C. Hwang and A. Wu, "A predictive system shutdown method for energy saving of event-driven computation," in Proc. Int. Conf. Computer-Aided Design (ICCAD), 1997, pp. 28-32.
24. M. Weiser, B. Welch, A. Demers, and S. Shenker, "Scheduling for reduced CPU energy," in Proc. USENIX Symp. Operating System Design Implementation, 1994, pp. 13-23.
25. F. Yao, A. Demers, and S. Shenker, "A scheduling model for reduced CPU energy," IEEE Annu. Found. Comput. Sci., pp. 374-382, 1995.
26. T. Tia, J. Liu, J. Sun, and R. Ha, "A linear-time optimal acceptance test for scheduling of hard real-time tasks," Dept. Comput. Sci., Univ. Illinois at Urbana-Champaign, Urbana-Champaign, IL, 1994.
27. G. Quan and X. S. Hu, "Energy efficient fixed-priority scheduling for real-time systems on voltage variable processors," in Proc. Design Automation Conf. (DAC), 2001, pp. 828-833.
28. I. Hong, D. Kirovski, O. Qu, M. Potkonjak, and M. B. Srivastava, "Power optimization of variable voltage core-based systems," in Proc. Design Automation Conf. (DAC), 1998, pp. 176-181.
29. I. Hong, G. Qu, M. Potkonjak, and M. B. Srivastava, "Synthesis techniques for low-power hard real-time systems on variable voltage processors," in Proc. Real-Time Systems Symp. (RTSS), 1998, pp. 178-187.
30. T. Ishihara and H. Yasuura, "Voltage scheduling problem for dynamically variable voltage processors," in Proc. Int. Symp. Low Power Electronics Design (ISLPED), Aug. 1998, pp. 197-202.
31. T. Okuma, T. Ishihara, and H. Yasuura, "Software energy reduction techniques for variable voltage processors," IEEE Design Test Comput., vol. 18, no. 2, pp. 31-41, Mar.-Apr. 2001.
32. V. Swaminathan and K. Chakrabarty, "Investigating the effect of voltage switching on low-energy task scheduling in hard real-time systems," in Proc. Asia and South Pacific (ASP)-Design Automation Conf. (DAC), June 2001, pp. 251-254.
33. H. Aydin, R. Melhem, D. Mossťe, and P. Alvarez, "Determining optimal processor speeds for periodic real-time tasks with different power characteristics," in Proc. 13th Euromicro Conf. Real-Time Systems (ECRTS), June 2001, pp. 225-232.
34. J. Liu, Real-Time Systems. Englewood Cliffs, NJ: Prentice-Hall, 2000.
35. G. Quan and X. Hu, "Minimum energy fixed-priority scheduling for variable voltage processors," in Proc. Design Automation Test (DATE) Conf., 2002, pp. 782-787.
36. D. Shin, J. Kim, and S. Lee, "Intra-task voltage scheduling for low-energy hard real-time applications," IEEE Design Test Comput., vol. 18, no. 2, pp. 20-30, Mar.-Apr. 2001.