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Volumn , Issue , 2003, Pages 138-146

Semiconductor process and device modeling: A graduate course / undergraduate elective in microelectronic engineering at RIT

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ENGINEERING EDUCATION; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON;

EID: 0042440988     PISSN: 07496877     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (2)

References (13)
  • 1
    • 0032670441 scopus 로고    scopus 로고
    • Exploring silicon process technology through RIT's NPN BJT process
    • K.D. Hirschman and P.D. Rack, "Exploring Silicon Process Technology Through RIT's NPN BJT Process," IEEE UGIM Symp. Proc. 13, 94 (1999).
    • (1999) IEEE UGIM Symp. Proc. , vol.13 , pp. 94
    • Hirschman, K.D.1    Rack, P.D.2
  • 5
    • 0039956433 scopus 로고
    • Generalized guide to MOSFET miniaturization
    • J.R. Brews et al., "Generalized Guide to MOSFET Miniaturization," IEEE Electron Dev. Letts., EDL-1, 2 (1980).
    • (1980) IEEE Electron Dev. Letts. , vol.EDL-1 , pp. 2
    • Brews, J.R.1
  • 6
    • 0035163958 scopus 로고    scopus 로고
    • An advanced CMOS process for university microelectronics laboratory courses
    • L.F. Fuller, "An Advanced CMOS process for University Microelectronics Laboratory Courses," IEEE UGIM Symp. Proc. 14, 36 (2001).
    • (2001) IEEE UGIM Symp. Proc. , vol.14 , pp. 36
    • Fuller, L.F.1
  • 7
    • 0041502030 scopus 로고    scopus 로고
    • http://smfl.microe.rit.edu
  • 9
    • 0034482809 scopus 로고    scopus 로고
    • A tolerance analysis for manufacturing to direct process capability improvement efforts
    • K.D. Hirschman, "A Tolerance Analysis for Manufacturing to Direct Process Capability Improvement Efforts," IEEE/SEMI ASMC Symp. Proc. 11, 377 (2000).
    • (2000) IEEE/SEMI ASMC Symp. Proc. , vol.11 , pp. 377
    • Hirschman, K.D.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.