Switch level fault simulation environment

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 780-785

  Krishnaswamy, V ^a   Casas, J ^a   Tetzlaff, T ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BENCHMARKING; COMPUTER SIMULATION; FAILURE ANALYSIS; LOGIC CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; SWITCHING CIRCUITS;

FAULT SIMULATION ALGORITHM; LOGIC BRIDGE MODEL; REGISTER TRANSFER LEVEL; SWITCH LEVEL FAULT INJECTION;

INTEGRATED CIRCUIT TESTING;

EID: 0033681646     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)