Layout-specific circuit evaluation in 3-D integrated circuits

Analog Integrated Circuits and Signal Processing

Volumn 35, Issue 2-3, 2003, Pages 199-206

  Alam, Syed M ^a   Troxel, Donald E ^a   Thompson, Carl V ^a  

^a Massachusetts Institute of Technology Cambridge   (United States)

Author keywords

3 D integrated circuits; FPGA; IC performance comparison; Layout methodology; Reliability

Indexed keywords

COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS; INTEGRATED CIRCUIT LAYOUT; INTEGRATING CIRCUITS; LINEAR INTEGRATED CIRCUITS; SILICON WAFERS; THREE DIMENSIONAL; TWO DIMENSIONAL;

LAYOUT SPECIFIC CIRCUIT EVALUATION; THREE DIMENSIONAL INTEGRATED CIRCUITS; THREE DIMENSIONAL INTEGRATION TECHNOLOGY;

LINEAR NETWORK ANALYSIS;

EID: 0041848636     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1024190918668     Document Type: Article

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