Processing and scheduling components in an innovative network processor architecture

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 195-201

  Vlachos, K ^a   Nikolaou, N ^a   Orphanoudakis, T ^b   Perissakis, S ^b   Pnevmatikatos, D ^c   Kornaros, G ^b   Sanchez, J A ^a   Konstantoulakis, G ^d  

^a NOKIA RESEARCH CENTER   (United States)

^b Ellemedia Technologies   (United States)

^c TECHNICAL UNIVERSITY OF CRETE   (Greece)

^d InAccess Networks   (Greece)

Author keywords

Acceleration; Hardware; Intelligent networks; Job shop scheduling; Processor scheduling; Protocols; Reduced instruction set computing; Telecommunication traffic; Throughput; Traffic control

Indexed keywords

ACCELERATION; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DESIGN; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; HIGH SPEED NETWORKS; INTEGRATED CIRCUIT DESIGN; INTELLIGENT NETWORKS; JOB SHOP SCHEDULING; NETWORK PROTOCOLS; OPTIMIZATION; PACKET NETWORKS; REDUCED INSTRUCTION SET COMPUTING; SCHEDULING; SYSTEMS ANALYSIS; TELECOMMUNICATION TRAFFIC; THROUGHPUT; TRAFFIC CONTROL;

HIGH-LEVEL PROTOCOLS; INTERNAL RESOURCES; NETWORK PROCESSOR; NETWORK PROCESSOR ARCHITECTURES; PACKET PROCESSING; PROCESSOR SCHEDULING; STREAMING OPERATIONS; TRAFFIC-SHAPING;

NETWORK ARCHITECTURE;

EID: 55849139961     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183136     Document Type: Conference Paper

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