Efficient per-flow queueing in DRAM at OC-192 line rate using out-of-order execution techniques

IEEE International Conference on Communications

Volumn 7, Issue , 2001, Pages 2048-2052

  Nikologiannis, Aristides ^a,b   Katevenis, Manolis ^a,b  

^a INSTITUTE OF COMPUTER SCIENCE   (Greece)

^b UNIVERSITY OF CRETE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE DESCRIPTION LANGUAGES; PIPELINE PROCESSING SYSTEMS; QUALITY OF SERVICE; QUEUEING THEORY; ROUTERS; SWITCHES;

PER-FLOW QUEUEING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034857901     PISSN: 05361486     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICC.2001.937019     Document Type: Article

References (10)

1. Pipelined multi-queue management in a VLSI ATM switch chip with credit-based flow control
2. Beyond best effort: Router architectures for the differentiated services of tomorrow's internet
3. Buffer management schemes for supporting TCP in gigabit routers with per-flow queueing
4. A rigorous correctness proof of the Tomasulo scheduling algorithm with precise interrupts
5. A VLSI architecture for an 80 Gb/s ATM switch core
6. Design and evaluation of a DRAM-based shared memory ATM