CMOS FinFET fabricated on bulk silicon substrate

Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors

Volumn 24, Issue 4, 2003, Pages 351-356

  Yin, Huaxiang ^a   Xu, Qiuxia ^a  

^a INSTITUTE OF GEOLOGY AND GEOPHYSICS   (China)

Author keywords

Bulk silicon substrate; CMOS; Design; Device characteristics; Fabrication; FinFET; Groove

Indexed keywords

DESIGN; ELECTRIC PROPERTIES; ELECTRODES; MOSFET DEVICES; SILICON; SILICON ON INSULATOR TECHNOLOGY;

BULK SILICON SUBSTRATE; DEVICE CHARACTERISTICS;

CMOS INTEGRATED CIRCUITS;

EID: 0038796496     PISSN: 02534177     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (4)

1. Lindert N, Chang L, Choi Y K, et al. Sub-60-nm quasi-planar FinFETs fabricated using a simplified process. IEEE Electron. Device Lett, 2001, 22(10): 487
2. Huang X J, Lee W C, Kuo C, et al. Sub 50 nm FinFET: PMOS. Proc IEDM, 1999: 67
3. Yin Huaxiang, Xu Qiuxia. Structure design considerations of a sub-50 nm self-aligned double gates MOSFET. Chinese Journal of Semiconductors, 2002, 23(12): 1267
4. Claeys C, Vanhellemont J. Structural and electrical characterization of SWAMI for submicron technologies. Ext ABS of Spring of Meeting of The ECS, 1988, 140: 211