Development of improved thermal performance embedded heat slug plastic ball grid array package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1490-1497

  Zahn, Bret A ^a   Carson, Flynn ^a   Lee, T K ^a   Coronado, Ray ^a   Mitchell, Dianne ^a  

^a ChipPAC Incorporated   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; EPOXY RESINS; FINITE ELEMENT METHOD; INTEGRATED CIRCUIT TESTING; LAMINATES; MATERIALS TESTING; MOLDS; SUBSTRATES; THERMODYNAMIC PROPERTIES;

HEAT SLUG; PLASTIC BALL GRID ARRAY PACKAGE; THERMAL PERFORMANCE; THERMALLY ENHANCED PACKAGE;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0038688774     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. Mulgaonker, S., Chambers, B., and Mahalingam, M., "An Assessment of the Thermal Performance of the PBGA Family," Proceedings of 11th IEEE Semi-Therm Symposium, pp. 17-27, 1995.
2. Johnson, Z., Ramakrishna, K., Joiner, B., and Eyman, M., "Thermal Sub-Modeling of the Wirebond Plastic Ball Grid Array Package," Proceedings of 13th IEEE Semi-Thermal Symposium, pp. 1-9, 1997.
3. Johnson, Z., and Eyman, M., "Design-Based Thermal Simulation Methodology for Ball Grid Array Packages," Proceedings of 6th Intersociety Conference on Thermal and Thermo-Mechanical Phenomena, pp. 82-87, 1998.
4. Eyman, M., Johnson, Z., and Joiner, B., "Thermal Simulation and Validation of the Fast Static RAM 164-Lead FC-PBGA Package with Investigation of Package Thermal Performance in a Generic CPU Module," Proceedings of 48th Electronic Components & Technology Conference, 1998.
5. Ramakrishna, K., Thomas, T.R., Lee, T.Y. Tom, Trent, J.R., and Hause, J.V., "Thermal Performance of an Air-Cooled Plastic Ball Grid Array Package in Natural and Forced Convection," Proceedings of 6th Intersociety Conference on Thermal and Thermo-Mechanical Phenomena, pp 27-34, 1998.
6. Zahn, B.A., "Steady-State Thermal Characterization and Junction Temperature Estimation of Multi-Chip Module Packages Using the Response Surface Method," Proceedings of 6th Intersociety Conference on Thermal and Thermo-Mechanical Phenomena, pp. 76-81, 1998.
7. Swaminath, P., Carson, F., Lee, T.K., Lee, H.T., "Thermally Enhanced PBGA Package Characterization, Thermal Performance and Reliability at High Temperatures (Pb-Free)," Proceedings of 35th International Symposium on Microelectronics, 2002.
8. JEDEC Specification EIA/JESD51-4: Thermal Test Chip Guideline (Wirebond Type Chip).
9. JEDEC Specification JESD51-9: Test Board for Area Array Surface Mount Package Thermal Measurements.
10. Zahn, B.A., Stout, R.P., "Evaluation of Isothermal and Isoflux Natural Convection Coefficient Correlations for Utilization in Electronic Package Level Thermal Analysis," Proceedings of 13th IEEE Semi-Therm Symposium, 1997.
11. Zahn, B.A., Stout, R.P., and Billings, D.T., "A Thermal Comparative Study of a Ceramic Dual In-Line Pressed Microelectronics Package Using Both Computational Fluid Dynamics and Solid Modeling Techniques on the ANSYS Finite Element Analysis System", Proceedings of 7th International ANSYS Conference and Exhibition, January 1996.
12. JEDEC Specification EIA/JESD51-2: Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air).
13. JEDEC Specification JESD51-6: Integrated Circuits Thermal Test Method Environmental Conditions - Forced Convection (Moving Air).
14. JEDEC Specification JESD51-8: Integrated Circuits Thermal Test Method Environmental Conditions - Junction-to-Board.