A 16mb cache DRAM LSI with internal 35.8GB/s memory bandwidth for simultaneous read and write operation

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 398-399

  Nakayama, M ^a   Sakakibara, H ^a   Kusunoki, M ^a   Kurita, K ^a   Yokoyama, Y ^a   Miyaoka, S ^a   Koike, J I ^a   Tamba, N ^a   Kobayashi, T ^a   Kume, M ^a   Sawamoto, H ^a   Kawata, A ^a   Tanaka, H ^a   Takada, Y ^a   Yamamoto, M ^a   Yagyu, M ^a   Tsuchiya, Y ^a   Yoshida, H ^a   Kitamura, N ^a   Yamaguchi, K ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY; FLIP FLOP CIRCUITS; LSI CIRCUITS; MACROS; MULTIPLEXING;

DATA BUSES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034430975     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. An ASIC library granular DRAM macro with built-in self test
2. 64Mb 6.8ns random ROW access DRAM macro for ASICs
3. A 12ns 8MB DRAM secondary cache for a 64b microprocessor
4. 2 stacked DRAM technology integrated with a high-performance 0.2μm logic and 6-level metalization