A 1.8-V embedded 18-Mb DRAM macro with a 9-ns RAS access time and memory-cell area efficiency of 33%

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 3, 2001, Pages 503-509

  Yokoyama, Yuji ^a   Itoh, Nobutaka ^a   Hasegawa, Masatoshi ^a   Katayama, Masahiro ^a   Akasaki, Hiroshi ^a   Kaneda, Masayuki ^a   Ueda, Toshitsugu ^a   Tanaka, Yousuke ^a   Yamasaki, Eiji ^a   Todokoro, Masaya ^a   Toriyama, Keinosuke ^a   Miki, Hiroshi ^a   Yagyu, Masayoshi ^a   Takashima, Kazumasa ^a   Kobayashi, Toru ^a   Miyaoka, Syuichi ^a   Tamba, Nobuo ^a  

^a HITACHI LTD   (Japan)

Author keywords

Amplifiers; Architecture redundancy; Capacitors; DRAM chips; High speed integrated circuits; Noise; Voltage control

Indexed keywords

AMPLIFIERS (ELECTRONIC); CAPACITORS; INTEGRATED CIRCUIT LAYOUT; MACROS; REDUNDANCY; VOLTAGE CONTROL;

HIGH SPEED INTEGRATED CIRCUITS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035273849     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.910489     Document Type: Article

References (6)

1. 64-Mb 6.8-ns random ROW access DRAM macro for ASICs
2. A 250-Mb/s/pin 1-Gb double data rate SDRAM with a bidirectional delay and an interbank shared redundancy scheme
3. A 256-Mb SDRAM with subthreshold leakage current suppression
4. 2 stacked DRAM technology integrated with a high-performance 0.2-μm logic and six-level metallization
5. An experimental 1.5-V 64-Mb dram
6. A 16-MB cache DRAM LSI with internal 35.8-GB/s memory bandwidth for simultaneous READ and WRITE operation