Comparative characteristics of on-chip single- and double-level square inductors

IEEE Transactions on Magnetics

Volumn 39, Issue 3 II, 2003, Pages 1778-1783

  Yin, W Y ^a   Pan, S J ^a   Li, L W ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b SINGAPORE MIT ALLIANCE   (Singapore)

Author keywords

Inductance; On chip single level (SL) and double level (DL) square inductors; Q factor; Resonance frequency

Indexed keywords

CAPACITANCE; DEGRADATION; INDUCTANCE; INTEGRATED CIRCUITS; MAGNETIC COUPLINGS; NATURAL FREQUENCIES; RESONANCE; SEMICONDUCTING SILICON; SUBSTRATES;

DOUBLE LEVEL SQUARE INDUCTORS; ON CHIP SINGLE LEVEL; Q FACTOR; RESONANCE FREQUENCY;

ELECTRIC INDUCTORS;

EID: 0038521249     PISSN: 00189464     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMAG.2003.809860     Document Type: Article

References (11)

1. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF IC's," IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.
2. M. Park, S. Lee, C. S. Kim, H. K. Yu, and K. S. Nam, "The detailed analysis of high Q CMOS-compatible microwave spiral inductors in silicon technology," IEEE Trans. Electron Devices, vol. 45, pp. 1953-1959, Sept. 1998.
3. P. Mernyei, F. Darrer, M. Pardoen, and A. Sibrai, "Reducing the substrate losses of RF integrated inductors," IEEE Microwave Guided Wave Lett., vol. 8, pp. 300-301, Sept. 1998.
4. A. M. Niknejad and R. G. Meyer, "Analysis, design, and optimization of spiral inductors and transformers for Si RF IC's," IEEE J. Solid-State Circuits, vol. 33, pp. 1470-1481, Oct. 1998.
5. P. Arcioni, R. Castello, G. De Astis, E. Sacchi, and F. Svelto, "Measurement and modeling of Si integrated inductors," IEEE Trans. Instrum. Meas., vol. 47, pp. 1372-1378, Oct. 1998.
6. S. S. Mohan, M. D. M. Heshenson, S. P. Boyd, and T. H. Lee, "Simple accurate expressions for planar spiral inductors," IEEE J. Solid-State Circuits, vol. 34, pp. 1419-1424, Oct. 1999.
7. P. Arcioni, R. Castello, L. Perregrini, E. Sacchi, and F. Svelto, "An innovative modelization of loss mechanisms in silicon integrated inductors," IEEE Trans. Circuits Syst. II, vol. 46, pp. 1453-1459, Dec. 1999.
8. C. P. Yue and S. S. Wong, "Physical modeling of spiral inductors on silicon," IEEE Trans. Electron Devices, vol. 47, pp. 560-568, Mar. 2000.
9. J. M. Lopez-Villegas, J. Samitier, C. Cane, P. Losantos, and J. Bausells, "Improvement of the quality factor of RF integrated inductors by layout optimization," IEEE Trans. Microwave Theory Tech., vol. 48, pp. 76-83, Jan. 2000.
10. Y. K. Koutsoyannopoulos and Y. Papananos, "Systematic analytic and modeling of integrated inductors and transformers in RFIC design," IEEE Trans. Circuits Syst. II, vol. 47, pp. 699-713, Aug. 2000.
11. A. Zolfaghari, A. Chan, and B. Razavi, "Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, pp. 620-628, Apr. 2001.