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Volumn 38, Issue 7, 2003, Pages 1242-1249

Globally updated mesochronous design style

Author keywords

Design methodology; Integrated circuits; Mesochronous; Metastability; Synchronization; System on chip (SoC); Timing

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCIES; SYNCHRONIZATION; TIMING CIRCUITS; VLSI CIRCUITS;

EID: 0038494078     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.813251     Document Type: Article
Times cited : (13)

References (9)
  • 1
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    • S. Hauck, "Asynchronous design methodologies: An overview," Proc. IEEE, vol. 83, pp. 69-93, Jan. 1995.
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    • Hauck, S.1
  • 4
    • 0035696292 scopus 로고    scopus 로고
    • A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnect
    • Dec.
    • H. Wilson and M. Haycock, "A six-port 30-GB/s nonblocking router component using point-to-point simultaneous bidirectional signaling for high-bandwidth interconnect," IEEE J. Solid State Circuits, vol. 36, pp. 1954-1963, Dec. 2001.
    • (2001) IEEE J. Solid State Circuits , vol.36 , pp. 1954-1963
    • Wilson, H.1    Haycock, M.2
  • 5
    • 0035245686 scopus 로고    scopus 로고
    • Self-tested self-synchronization circuit for mesochronous clocking
    • Feb.
    • F. Mu and C. Svensson, "Self-tested self-synchronization circuit for mesochronous clocking," IEEE Trans. Circuits Syst. II, vol. 48, pp. 129-140, Feb. 2001.
    • (2001) IEEE Trans. Circuits Syst. II , vol.48 , pp. 129-140
    • Mu, F.1    Svensson, C.2
  • 6
    • 0030655274 scopus 로고    scopus 로고
    • Hierarchical synchronization scheme using self-timed mesochronous interconnection
    • June
    • S. Kim and R. Sridhar, "Hierarchical synchronization scheme using self-timed mesochronous interconnection," in Proc. IEEE Int. Symp. Circuits and Systems, vol. 3, June 1997, pp. 1824-1827.
    • (1997) Proc. IEEE Int. Symp. Circuits and Systems , vol.3 , pp. 1824-1827
    • Kim, S.1    Sridhar, R.2
  • 7
    • 25944454677 scopus 로고    scopus 로고
    • Expandable high throughput vector based access memory architecture
    • Sept.
    • I. Söderquist, "Expandable high throughput vector based access memory architecture," in Proc. 28th Eur. Solid-State Circuit Conf., Sept. 2002, pp. 599-602.
    • (2002) Proc. 28th Eur. Solid-State Circuit Conf. , pp. 599-602
    • Söderquist, I.1
  • 9
    • 0023436314 scopus 로고
    • A true single-phase-clock dynamic CMOS circuit technique
    • Oct.
    • Y. Ji-Ren, I. Karlsson, and C. Svensson, "A true single-phase-clock dynamic CMOS circuit technique." IEEE J. Solid-State Circuits, vol. SC-22, pp. 899-901, Oct. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , pp. 899-901
    • Ji-Ren, Y.1    Karlsson, I.2    Svensson, C.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.