Expandable high throughput vector based access memory architecture

European Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 599-602

  Soderquist, Ingemar ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BI-CMOS PROCESS; DISTRIBUTED CONTROL LOGIC; HIGH THROUGHPUT; NETWORK ROUTERS; OPERATION FREQUENCY; PROTOTYPE CHIP; RESEARCH DESIGNS; WARFARE APPLICATIONS;

BICMOS TECHNOLOGY; ELECTRONIC WARFARE; MICROPROCESSOR CHIPS;

MEMORY ARCHITECTURE;

EID: 25944454677     PISSN: 19308833     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. H. Kim and I.-C. Park, "High-Performance and Low-Power Memory-Interface Architecture for Video Processing Applications," IEEE Transaction on circuits and systems for video technology, vol. 11, no. 11, pp. 1160-1170, Nov 2001.
3. W. A. White, A. H. Taddiken, H. Shichijo, M. A. Vernon and D. A. Whitmere, "Design and Application of a GaAs Digital RF Memory Chip," IEEE Journal of Solid State Circuits, vol. 25, no. 4, pp. 961-970, Aug. 1990.
4. M. A. Mehalic and A. M. Sayson, "A Dual-port DRAM Component for a Digital RF Memory," Aerospace and Electronics Conference, 1992. NAECON 1992., Proceedings of the National, pp. 85-89, May. 1992.
5. I. Söderquist, "Memory structure," Swedish patent no. SE9502113-5, publication number 514348.
6. I. Söderquist, "Clock signal distribution and synchronization in a digital system," patent no. US005982238A.
7. P. Ingelhag, I. Söderquist, and R Sundblad, "A 200 MHz CMOS digital radio frequency memory chip with analog output," CICC 1993, San Diego, Califonia, May 9-12, 1993.
8. Y. Ji-Ren, I. Karlsson, and C. Svensson, "A true singlephase-clock dynamic CMOS circuit technique," IEEE J. Solid-State Circuits, vol. 22, pp. 899-901, Oct. 1987.