Integrated floorplanning with buffer/channel insertion for bus-based designs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 22, Issue 6, 2003, Pages 730-741

  Rafiq, Faran ^a,b   Chrzanowska Jeske, Malgorzata ^a   Yang, Hannah Honghua ^b   Jeske, Marcin ^c,d   Sherwani, Naveed ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b INTEL CORPORATION   (United States)

^c Intel Corporation ^*  (United States)

^d PORTLAND STATE UNIVERSITY   (United States)

Author keywords

Buffers; Floorplanning; Graph theory; Integrated circuit layout; Linear integer programming; Simulated annealing

Indexed keywords

ALGORITHMS; GRAPH THEORY; INTEGER PROGRAMMING; INTEGRATED CIRCUIT LAYOUT; LINEAR PROGRAMMING; PROBLEM SOLVING; SIMULATED ANNEALING;

BUS-BASED DESIGNS;

COMPUTER AIDED DESIGN;

EID: 0038380285     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.811443     Document Type: Conference Paper

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