Fast and accurate estimation of floorplans in logic/high-level synthesis

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2000, Pages 95-100

  Bazargan, Kiarash ^a   Ranjan, Abhishek ^a   Sarrafzadeh, Majid ^a  

^a NORTHWESTERN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ESTIMATION; FORMAL LOGIC;

ENGINEERING CHANGE ORDER (ECO); HIGH-LEVEL SYNTHESIS (HLS);

MICROPROCESSOR CHIPS;

EID: 0033700489     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/330855.330990     Document Type: Conference Paper

References (12)