Optimal FPGA mapping and retiming with efficient initial state computation

Proceedings - Design Automation Conference

Volumn , Issue , 1998, Pages 330-335

  Cong, Jason ^a   Wu, Chang ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); MAPPING; POLYNOMIAL APPROXIMATION; ALGORITHMS; COMPUTATIONAL COMPLEXITY; POLYNOMIALS; SEQUENTIAL CIRCUITS; STATE ASSIGNMENT;

CLOCK PERIOD; CONVENTIONAL APPROACH; INITIAL STATE; NP-HARD; POLYNOMIAL-TIME ALGORITHMS; RETIMING;

OPTIMIZATION; FIELD PROGRAMMABLE GATE ARRAYS;

POLYNOMIAL TIME ALGORITHMS;

EID: 0031623039     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/277044.277139     Document Type: Conference Paper

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