Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 1916-1918

  Masahara, Meishoku ^a   Matsukawa, Takashi ^a   Ishii, Kenichi ^a   Liu, Yongxun ^a   Nagao, Masayoshi ^a   Tanoue, Hisao ^a   Tanii, Takashi ^b   Ohdomari, Iwao ^b   Kanemaru, Seigo ^a   Suzuki, Eiichi ^a  

^a NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY AIST   (Japan)

^b WASEDA UNIVERSITY   (Japan)

Author keywords

Ion implantation; Ion bombardment retarded etching of Si; TMAH; Ultrathin Si wall; Vertical double gate MOSFET; Wet etching

Indexed keywords

AMMONIUM COMPOUNDS; DRY ETCHING; ION BOMBARDMENT; ION IMPLANTATION; SILICON WAFERS; SOLUTIONS;

TETRAMETHYLAMMONIUM HYDROXIDE; ULTRATHIN SILICON WALL; VERTICAL DOUBLE-GATE MOSFET;

MOSFET DEVICES;

EID: 0038348097     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.42.1916     Document Type: Article

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