High performance 40 nm vertical MOSFET within a conventional CMOS process flow

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue TECHNOLOGY SYMP., 2001, Pages 55-56

  Josse, E ^a   Skotnicki, T ^a   Jurczak, M ^a   Paoli, M ^a   Tormen, B ^a   Dutartre, D ^a   Ribot, P ^a   Villaret, A ^a   Sondergard, E ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL CAPACITY; CMOS INTEGRATED CIRCUITS; DIELECTRIC MATERIALS; FABRICATION; GATES (TRANSISTOR); SEMICONDUCTING SILICON; SEMICONDUCTOR DOPING;

PROCESS FLOW;

MOSFET DEVICES;

EID: 0034795203     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Short course