A 10 b 120 Msample/s time-interleaved analog-to-digital converter with digital background calibration

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2002, Pages 172-173+457+165

  Jamal, Shafiq M ^a   Fu, Daihong ^a   Hurst, Paul J ^a   Lewis, Stephen H ^a  

^a MARVELL SEMICONDUCTOR INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALIBRATION; CORRELATION METHODS; FEEDBACK; FIR FILTERS; NATURAL FREQUENCIES; PHASE MODULATION;

SAMPLE-AND-HOLD AMPLIFIERS (SHA);

ANALOG TO DIGITAL CONVERSION;

EID: 0036113498     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. Time interleaved converter arrays
2. An 8-b 85-MS/s parallel pipeline A/D converter in 1-μm CMOS
3. A 10-bit 200-MS/s CMOS parallel pipeline A/D converter
4. A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs
5. A digital background calibration technique for time-interleaved analog-to-digital converters
6. 2