An intelligent cache system with hardware prefetching for high performance

IEEE Transactions on Computers

Volumn 52, Issue 5, 2003, Pages 607-616

  Lee, Jung Hoon ^a   Jeong, Seh Woong ^b   Kim, Shin Dug ^a   Weems, Charles C ^c  

^a Yonsei University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

^c University of Massachusetts Amherst   (United States)

Author keywords

Dual data cache; Memory hierarchy; Prefetching; Spatial locality; Temporal locality

Indexed keywords

OPTIMIZATION; PROGRAM COMPILERS; VECTORS;

HARDWARE PREFETCHING;

CACHE MEMORY;

EID: 0038294686     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2003.1197127     Document Type: Article

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