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Volumn 46, Issue 15, 2000, Pages 1451-1467

A new cache architecture based on temporal and spatial locality

Author keywords

Cache simulation; Dual data cache; Memory hierarchy; Spatial locality; Temporal locality

Indexed keywords

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; EMBEDDED SYSTEMS; HIERARCHICAL SYSTEMS;

EID: 0034500182     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/S1383-7621(00)00035-7     Document Type: Article
Times cited : (17)

References (19)
  • 2
    • 0029192697 scopus 로고    scopus 로고
    • Cache design tradeoffs for power and performance optimization: A case study
    • Dana Point, CA
    • C. Su, A. Despain, Cache design tradeoffs for power and performance optimization: A case study, ACM/IEEE International Symposium on Low-Power Design, Dana Point, CA (1996) 63-68.
    • (1996) ACM/IEEE International Symposium on Low-Power Design , pp. 63-68
    • Su, C.1    Despain, A.2
  • 6
    • 0029204095 scopus 로고
    • Data cache with multiple caching strategies tuned to different types of locality
    • Gonzalez A., Aliagas C., Mateo M. Data cache with multiple caching strategies tuned to different types of locality. Supercomputing '95. 1995;338-347.
    • (1995) Supercomputing '95 , pp. 338-347
    • Gonzalez, A.1    Aliagas, C.2    Mateo, M.3
  • 7
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers
    • Jouppi N.P. Improving direct-mapped cache performance by the addition of a small fully associative cache and prefetch buffers. 17th ISCA. 1990;364-373.
    • (1990) 17th ISCA , pp. 364-373
    • Jouppi, N.P.1
  • 8
    • 0008574019 scopus 로고
    • PA-7200: A PA-RISC processor with integrated high performance MP bus interface
    • Kurpanchek G.et al. PA-7200: A PA-RISC processor with integrated high performance MP bus interface. COMPCON Digest of Papers. 1994;375-382.
    • (1994) COMPCON Digest of Papers , pp. 375-382
    • Kurpanchek, G.1
  • 13
    • 0025429332 scopus 로고
    • The performance impact of block sizes and fetch strategies
    • Przybylski S. The performance impact of block sizes and fetch strategies. 17th ISCA. 1990;160-169.
    • (1990) 17th ISCA , pp. 160-169
    • Przybylski, S.1
  • 14
    • 0031334222 scopus 로고    scopus 로고
    • Static locality analysis for cache management
    • Jesus Sanchez F., Gonzalez A., Valeo M. Static locality analysis for cache management. PACT'97. 1997;261-271.
    • (1997) PACT'97 , pp. 261-271
    • Jesus Sanchez, F.1    Gonzalez, A.2    Valeo, M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.