-
1
-
-
0025429331
-
Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers
-
May
-
N. Jouppi, "Improving Direct-Mapped Cache Performance by the Addition of a Small Fully-Associative Cache and Prefetch Buffers," Proc. 17th Int'l Symp. Computer Architecture, pp. 364-373, May 1990.
-
(1990)
Proc. 17th Int'l Symp. Computer Architecture
, pp. 364-373
-
-
Jouppi, N.1
-
3
-
-
0020177251
-
Cache Memories
-
Sept.
-
A. Smith, "Cache Memories," Computing Surveys, vol. 14, pp. 473-530, Sept. 1982.
-
(1982)
Computing Surveys
, vol.14
, pp. 473-530
-
-
Smith, A.1
-
4
-
-
0024173488
-
A Case for Direct-Mapped Caches
-
Dec.
-
M. Hill, "A Case for Direct-Mapped Caches," Computer, vol. 21, no. 12, pp. 25-40, Dec. 1988.
-
(1988)
Computer
, vol.21
, Issue.12
, pp. 25-40
-
-
Hill, M.1
-
5
-
-
0023708930
-
Performance Tradeoffs in Cache Design
-
June
-
S. Przybylski, M. Howrowitz, and J. Hennessy, "Performance Tradeoffs in Cache Design," Proc. 15th Int'l Symp. Computer Architecture, pp. 290-298, June 1988.
-
(1988)
Proc. 15th Int'l Symp. Computer Architecture
, pp. 290-298
-
-
Przybylski, S.1
Howrowitz, M.2
Hennessy, J.3
-
8
-
-
0027192667
-
Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches
-
May
-
A. Agarwal and S. Pudar, "Column-Associative Caches: A Technique for Reducing the Miss Rate of Direct-Mapped Caches," Proc. 20th Int'l Symp. Computer Architecture, pp. 179-190, May 1993.
-
(1993)
Proc. 20th Int'l Symp. Computer Architecture
, pp. 179-190
-
-
Agarwal, A.1
Pudar, S.2
-
9
-
-
0002662988
-
The Alpha AXP Architecture and 21064 Processor
-
June
-
E. McLellan, "The Alpha AXP Architecture and 21064 Processor," IEEE Micro, vol. 13, no. 3, pp. 36-47, June 1993.
-
(1993)
IEEE Micro
, vol.13
, Issue.3
, pp. 36-47
-
-
McLellan, E.1
-
10
-
-
0026904396
-
An Analytical Access Time Model for On-Chip Cache Memories
-
T. Wada, S. Rajan, and S. Przybylski, "An Analytical Access Time Model for On-Chip Cache Memories," IEEE J. Solid-State Circuits, vol. 27, no. 8, 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.8
-
-
Wada, T.1
Rajan, S.2
Przybylski, S.3
-
13
-
-
85087536972
-
Generation and Analysis of Very Long Address Traces
-
June
-
D. Wall, A. Borg, and R. Kessler, "Generation and Analysis of Very Long Address Traces," Proc. 17th Int'l Symp. Computer Architecture, pp. 290-298, June 1990.
-
(1990)
Proc. 17th Int'l Symp. Computer Architecture
, pp. 290-298
-
-
Wall, D.1
Borg, A.2
Kessler, R.3
-
16
-
-
0012529383
-
BACH: A Hardware Monitor for Tracing Microprocessor-Based Systems
-
Oct.
-
K. Grimsrud, J. Archibald, M. Ripley, and K. Flanagan, "BACH: A Hardware Monitor for Tracing Microprocessor-Based Systems," Microprocessors and Microsystems, vol. 17, pp. 443-459, Oct. 1993.
-
(1993)
Microprocessors and Microsystems
, vol.17
, pp. 443-459
-
-
Grimsrud, K.1
Archibald, J.2
Ripley, M.3
Flanagan, K.4
-
17
-
-
33747396714
-
Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches
-
U.C. Santa Cruz
-
D. Stiliadis and A. Varma, "Selective Victim Caching: A Method to Improve the Performance of Direct-Mapped Caches," Tech. Rep. UCSC-CRL-93-41, U.C. Santa Cruz, 1993 (http:/ / www.cse.ucsc.edu/ research/ hsnlab/ publications.html).
-
(1993)
Tech. Rep. UCSC-CRL-93-41
-
-
Stiliadis, D.1
Varma, A.2
|