Power/performance advantages of victim buffer in high-performance processors

Proceedings - IEEE Alessandro Volta Memorial Workshop on Low-Power Design, VOLTA 1999

Volumn , Issue , 1999, Pages 43-51

  Albera, Gianluca ^a,b   Bahar, R Iris ^b  

^a POLITECNICO DI TORINO   (Italy)

^b BROWN UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION;

ARCHITECTURAL LEVELS; CACHE CONFIGURATIONS; CACHE ENERGY CONSUMPTION; HIGH PERFORMANCE PROCESSORS; LOW POWER MICROPROCESSORS; MEMORY HIERARCHY; PERFORMANCE GAIN; VICTIM BUFFER;

EMBEDDED SYSTEMS;

EID: 77953483477     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPD.1999.750402     Document Type: Conference Paper

References (12)

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