Array pass transistor design in trench cell for Gbit DRAM and beyond

International Symposium on VLSI Technology, Systems, and Applications, Proceedings

Volumn , Issue , 1999, Pages 251-254

  Li, Y ^a   Mandelman, J ^a   Parries, P ^a   Matsubara, Y ^a   Ye, Q ^a   Rengarajan, R ^a   Alsmeier, J ^a   Flietner, B ^a   Wheeler, D ^a   Akatsu, H ^a   Divakaruni, R ^a   Mohler, R ^a   Sunouchi, K ^a   Bronner, G ^a   Chen, T C ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

ARRAY PASS TRANSISTOR DESIGN; BIASING; ELECTRICAL CHARACTERIZATION; JUNCTION LEAKAGE; TRENCH CELL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0032599150     PISSN: 1524766X     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (7)