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Volumn 89, Issue 11, 2002, Pages 821-831

Unified MOSFET scaling theory using the variational method

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; COMPUTER SIMULATION; GATES (TRANSISTOR); POISSON EQUATION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SILICON ON INSULATOR TECHNOLOGY; TWO DIMENSIONAL; VARIATIONAL TECHNIQUES;

EID: 0038127214     PISSN: 00207217     EISSN: None     Source Type: Journal    
DOI: 10.1080/0020721031000104478     Document Type: Article
Times cited : (2)

References (12)
  • 1
    • 0031079417 scopus 로고    scopus 로고
    • Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFET's
    • Auth, C. P., and Plummer, J. D., 1997, Scaling theory for cylindrical, fully depleted, surrounding-gate MOSFET's. IEEE Electron Device Letters, 18, 74-76.
    • (1997) IEEE Electron Device Letters , vol.18 , pp. 74-76
    • Auth, C.P.1    Plummer, J.D.2
  • 3
    • 0032048034 scopus 로고    scopus 로고
    • A new deduction of the threshold voltage for short-channel FDSOI MOSFET's using parabolic potential approach
    • Chen, W. S., Tian, L. L., Yu, Z. P., and Li, Z. J., 1998, A new deduction of the threshold voltage for short-channel FDSOI MOSFET's using parabolic potential approach. Chinese Journal of Electronics, 17, 152-157.
    • (1998) Chinese Journal of Electronics , vol.17 , pp. 152-157
    • Chen, W.S.1    Tian, L.L.2    Yu, Z.P.3    Li, Z.J.4
  • 4
    • 0028448562 scopus 로고
    • Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements
    • Fiegan, C., Iwai, H., Wada, T., Saito, M., Sangiorgi, E., and Ricco, B., 1994, Scaling the MOS transistor below 0.1 μm: Methodology, device structures, and technology requirements. IEEE Transactions on Electron Devices, 41, 941-950.
    • (1994) IEEE Transactions on Electron Devices , vol.41 , pp. 941-950
    • Fiegan, C.1    Iwai, H.2    Wada, T.3    Saito, M.4    Sangiorgi, E.5    Ricco, B.6
  • 5
    • 0032187666 scopus 로고    scopus 로고
    • Generalized scale length for two-dimensional effects in MOSFET's
    • Frank, D. J., Taur, Y., and Wong, H. P., 1998, Generalized scale length for two-dimensional effects in MOSFET's. IEEE Electron Device Letters, 19, 385-387.
    • (1998) IEEE Electron Device Letters , vol.19 , pp. 385-387
    • Frank, D.J.1    Taur, Y.2    Wong, H.P.3
  • 6
    • 0027657417 scopus 로고
    • A new 2D analytic threshold-voltage model for fully depleted short-channel SOI MOSFET's
    • Guo, J. Y., and Wu, C. Y., 1993, A new 2D analytic threshold-voltage model for fully depleted short-channel SOI MOSFET's, IEEE Transactions on Electron Devices, 40, 1653-1661.
    • (1993) IEEE Transactions on Electron Devices , vol.40 , pp. 1653-1661
    • Guo, J.Y.1    Wu, C.Y.2
  • 7
    • 0024737720 scopus 로고
    • MOSFET scaling limits determined by subthreshold conduction
    • Pimbley, J. M., and Meindl, J. D., 1989, MOSFET scaling limits determined by subthreshold conduction. IEEE Transactions on Electron Devices, 36, 1711-1720.
    • (1989) IEEE Transactions on Electron Devices , vol.36 , pp. 1711-1720
    • Pimbley, J.M.1    Meindl, J.D.2
  • 12
    • 0024612456 scopus 로고
    • Short-channel effect in fully depleted SOI MOSFET's
    • Young, K. K., 1989, Short-channel effect in fully depleted SOI MOSFET's. IEEE Transactions on Electron Devices, 36, 399-402.
    • (1989) IEEE Transactions on Electron Devices , vol.36 , pp. 399-402
    • Young, K.K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.