Minimizing concurrent test time in SoC's by balancing resource usage

GLSVLSI 2002 - Proceedings of the 12th ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2002, Pages 77-82

  Zhao, Dan ^a   Upadhyaya, Shambhu ^a   Margala, Martin ^b  

^a UNIVERSITY AT BUFFALO   (United States)

^b UNIVERSITY OF ROCHESTER   (United States)

Author keywords

Resource balancing; System on a chip test scheduling; Test sets selection

Indexed keywords

INTEGRATED CIRCUIT TESTING; PROGRAMMABLE LOGIC CONTROLLERS; SCHEDULING ALGORITHMS; VLSI CIRCUITS;

ALTERNATE TEST; CONCURRENT TEST; MULTIPLE TEST; RESOURCE USAGE; SYSTEM-ON-A-CHIP TEST; TEST APPLICATION TIME; TEST SCHEDULING ALGORITHM; TEST SETS;

SYSTEM-ON-CHIP;

EID: 0038111322     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/505306.505323     Document Type: Conference Paper

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