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Volumn 9, Issue 3, 2000, Pages 28-X1
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3-D stacked wafer-level packaging
a a a
a
NONE
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Author keywords
[No Author keywords available]
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Indexed keywords
CRYSTAL LATTICES;
HEAT RESISTANCE;
MULTICHIP MODULES;
PLASMA ETCHING;
SILICON WAFERS;
THERMAL CONDUCTIVITY;
THERMAL EXPANSION;
THICKNESS CONTROL;
WSI CIRCUITS;
WAFER LEVEL PACKAGING;
ELECTRONICS PACKAGING;
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EID: 0034149013
PISSN: 10650555
EISSN: None
Source Type: Trade Journal
DOI: None Document Type: Article |
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Times cited : (21)
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References (0)
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