Performance analysis of optimised CMOS comparator

Electronics Letters

Volumn 39, Issue 11, 2003, Pages 833-835

  Le, H P ^a   Zayegh, A ^a   Singh, J ^a  

^a VICTORIA UNIVERSITY   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

COMPARATOR CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

CIRCUIT OPTIMIZATION;

CMOS INTEGRATED CIRCUITS;

EID: 0037664868     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20030546     Document Type: Article

References (7)

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2. BONI, A., MORANDI, C., and PADOAN, S.: 'A 2.5-V BiCMOS comparator with current-mode interpolation', IEEE J. Solid-State Circuits, 1999, 34, (6), pp. 892-897
3. SOLDERA, J.D.B., and OKI, N.: 'A high speed 3.3 V current mode CMOS comparator with 10-b resolution'. Proc. 43rd IEEE Midwest Symp. on Circuits and Systems, Lansing, MI, USA, 2000, Vol. 2, pp. 1008-1009
4. DEMOSTHENOUS, A., and TAYLOR, J.: 'A 2.8 V 200 MHz replicating current comparator for convolution decoders'. Proc. IEEE European Solid-State Circuits Conf., Sweden, 2000, pp. 272-275
5. LE, H.P., ZAYEGH, A., and SINGH, J.: 'A high-speed low-power CMOS comparator with 10-bit resolution'. Proc. 4th Int. Conf. on Modeling and Simulation, MS'02, Melbourne, Australia, pp. 138-142
6. GRAY, P.G., HURST, P.J., LEWIS, S.H., and MEYER, R.G.: 'Analysis and design of analog integrated circuits' (John Wiley & Son Inc, USA, 2001, 4th edn.)
7. STOJCEVSKI, A., LE, H.P., ZAYEGH, A., and SINGH, J.: 'New flash ADC architecture', Electron. Lett., 2003, 39, (6), pp. 501-502