The influence of defects on compatibility and yield of the HfO2-polysilicon gate stack for CMOS integration

Materials Research Society Symposium - Proceedings

Volumn 745, Issue , 2002, Pages 335-340

  Kaushik, V S ^a   DeGendt, S ^b   Carter, R ^b   Claes, M ^b   Rohr, E ^b   Pantisano, L ^b   Kluth, J ^a   Kerber, A ^a   Cosnier, V ^a   Cartier, E ^a   Tsai, W ^a   Young, E ^a   Green, M ^a   Chen, J ^a   Jang, S A ^a   Lin, S ^a   Delabie, A ^b   Elshocht, S V ^b   Manabe, Y ^b   Richard, O ^b   Zhao, C ^b   Bender, H ^b   Caymax, M ^b   Heyns, M ^b   more..

^a SEMATECH   (United States)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITORS; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; CRYSTAL DEFECTS; HAFNIUM COMPOUNDS; MICROSCOPIC EXAMINATION; POLYSILICON;

EMISSION MICROSCOPY;

DIELECTRIC MATERIALS;

EID: 0037617682     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-745-n8.7/t6.7     Document Type: Conference Paper

References (6)

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3. M.Claes, T.Witters, G.Loriaux, S.Van Elshocht, A.Delabie, S.De Gendt, M.M.Heyns, and H.F.Okorn-Schmidt, "Open Circuit Potential Analysis as a fest screening method for the quality of high-K dielectric layers", Sixth International Symposium on Ultra-Clean Processing of Silicon Surfaces (UCPSS) (September 2002).
4. T.Hori, in Gate Dielectrics and MOS ULSIs - Principles, Technologies and Applications, 145, Springer-Verlag (1997).
5. 2 gate dielectrics", App. Phy. Lett. 81 (7) 1288 (2002).
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