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Volumn 22, Issue 5, 2003, Pages 535-544

Efficient canonical form for Boolean matching of complex functions in large libraries

Author keywords

Boolean function; Circuit design; Circuit optimization; Technology mapping

Indexed keywords

BOOLEAN FUNCTIONS; CONFORMAL MAPPING; EQUIVALENCE CLASSES; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; MATHEMATICAL TRANSFORMATIONS; OPTIMIZATION; RESPONSE TIME (COMPUTER SYSTEMS); TABLE LOOKUP;

EID: 0037515538     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2003.810744     Document Type: Article
Times cited : (26)

References (16)
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  • 7
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    • SIS: A system for sequential circuit synthesis
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    • (1992)
    • Sentovich, E.1
  • 10
    • 0003728037 scopus 로고
    • New York: McGraw-Hill; McGraw-Hill Series on Computer Engineering
    • S. Devadas, A. Ghosh, and K. Keutzer, Logic Synthesis. New York: McGraw-Hill, 1994, McGraw-Hill Series on Computer Engineering.
    • (1994) Logic Synthesis
    • Devadas, S.1    Ghosh, A.2    Keutzer, K.3
  • 11
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    • Permutation and phase independent boolean comparison
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  • 12
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    • Design and synthesis of dynamic circuits
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  • 14
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    • Boolean matching and level-based technology mapping
    • Ph.D. dissertation, Univ. of Washington, Dept. of Elec. Eng.
    • J. Ciric, "Boolean Matching and Level-Based Technology Mapping," Ph.D. dissertation, Univ. of Washington, Dept. of Elec. Eng., 2001.
    • (2001)
    • Ciric, J.1
  • 16
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    • Module clustering to minimize delay in digital networks
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.