Delay optimization of combinational logic circuits by clustering and partial collapsing

1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers

Volumn , Issue , 1992, Pages 188-191

  Touati, HerveJ ^a   Savoj, Hamid ^a   Brayton, Robert K ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; OPTIMIZATION;

COMBINATIONAL LOGIC CIRCUITS;

COMBINATORIAL CIRCUITS;

EID: 0027075807     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)