A hierarchical test generation approach using program slicing techniques on hardware description languages

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 19, Issue 2, 2003, Pages 149-160

  Vedula, Vivekananda M ^a   Abraham, Jacob A ^a   Bhadra, Jayanta ^b   Tupuri, Raghuram ^c  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b MOTOROLA INC   (United States)

^c ADVANCED MICRO DEVICES   (United States)

Author keywords

Constraint slicing; Data flow analysis; Hierarchical test generation; Incremental slicing; Program slicing

Indexed keywords

AUTOMATIC TESTING; BUILT-IN SELF TEST; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE DESCRIPTION LANGUAGES; CONSTRAINT THEORY; DATA FLOW ANALYSIS; DESIGN FOR TESTABILITY; EMBEDDED SYSTEMS; VLSI CIRCUITS;

CONSTRAINT SLICING; HIERARCHICAL TEST GENERATION; INCREMENTAL SLICING; PROGRAM SLICING; SEQUENTIAL AUTOMATIC TEST PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0037379267     PISSN: 09238174     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1022885523034     Document Type: Article

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