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Volumn 6, Issue 1, 1996, Pages 67-73

VLSI architectures for block matching algorithms using systolic arrays

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; DIGITAL COMMUNICATION SYSTEMS; DIGITAL SIGNAL PROCESSING; MATHEMATICAL MODELS; SYSTOLIC ARRAYS; VLSI CIRCUITS;

EID: 0030085283     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/76.486421     Document Type: Article
Times cited : (27)

References (23)
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.