6 Gbps CMOS phase detecting DEMUX module using half-frequency clock

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1998, Pages 196-197

  Nakamura, Kazuyuki ^a   Fukaishi, Muneo ^a   Abiko, Hitoshi ^a   Matsumoto, Akira ^a   Yotsuyanagi, Michio ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MULTIPLEXING; PHASE LOCKED LOOPS; TIMING CIRCUITS;

CLOCK RECOVERY CIRCUITS (CRC); DATA DEMULTIPLEXING; PHASE DETECTORS;

DETECTOR CIRCUITS;

EID: 0031641469     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)