0.6 μm CMOS 4 Gb/s transceiver with data recovery using oversampling

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1997, Pages 71-72

  Yang, Chih Kong Ken ^a   Farjad Rad, Ramin ^a   Horowitz, Mark ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; MULTIPLEXING EQUIPMENT; PHASE LOCKED LOOPS;

DATA RECOVERY;

TRANSCEIVERS;

EID: 0031343173     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)