A redundant multi-valued logic for 10Gb/s CMOS demultiplexer IC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 220-221+449

  Tanabe, A ^a   Nakahara, Y ^a   Furukawa, A ^a   Mogami, T ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BIT ERROR RATE; COMPARATOR CIRCUITS; DECODING; DEMULTIPLEXING; ELECTRIC POTENTIAL; FABRICATION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; PHASE LOCKED LOOPS; WAVEFORM ANALYSIS;

PSEUDO RANDOM BIT SEQUENCE (PRBS);

CMOS INTEGRATED CIRCUITS;

EID: 0035060906     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A 10Gb/s demultiplexer IC in 0.18μm CMOS using current mode logic with tolerance to the threshold voltage fluctuation
2. A 6Gbps CMOS phase detecting DEMUX module using half-frequency clock
3. A 0.8μm CMOS 2.5Gb/s oversampling receiver and transmitter for serial links