The GRD chip: Genetic reconfiguration of DSPs for neural network processing

IEEE Transactions on Computers

Volumn 48, Issue 6, 1999, Pages 628-639

  Murakawa, Masahiro ^b   Yoshizawa, Shuji ^a,c   Kajitani, Isamu ^d   Yao, Xin ^a,e   Kajihara, Nobuki ^f   Iwata, Masaya ^b   Higuchi, Tetsuya ^b  

^a IEEE

^b ELECTROTECHNICAL LABORATORY   (Japan)

^c UNIVERSITY OF TOKYO   (Japan)

^d UNIVERSITY OF TSUKUBA   (Japan)

^e UNIVERSITY OF NEW SOUTH WALES   (Australia)

^f NEC CORPORATION   (Japan)

Author keywords

Digital signal processor; Evolvable hardware; Genetic algorithm; Neural network; Nonlinear adaptive equalization; RBF network; Time series prediction

Indexed keywords

COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; ELECTRIC NETWORK TOPOLOGY; GENETIC ALGORITHMS; NEURAL NETWORKS; REDUCED INSTRUCTION SET COMPUTING;

DIGITAL SIGNAL PROCESSOR; EVOLVABLE HARDWARE; GENETIC RECONFIGURATION OF DIGITAL SIGNAL PROCESSING; NONLINEAR ADAPTIVE EQUALIZATION; TIME SERIES PREDICTION;

MICROPROCESSOR CHIPS;

EID: 0032686680     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.773799     Document Type: Article

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