A CMOS neuron for VLSI circuit implementation of pulsed neural networks

IECON Proceedings (Industrial Electronics Conference)

Volumn 4, Issue , 2002, Pages 3182-3185

  Liu, Bo ^a   Frenzel, James F ^a  

^a UNIVERSITY OF IDAHO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; DIGITAL CIRCUITS; NEURAL NETWORKS; PULSE WIDTH MODULATION; VLSI CIRCUITS; WAVEFORM ANALYSIS;

DIGITAL WEIGHTS; NEURON ACTIVATION; NEURONS; PULSED NEURAL NETWORKS; SYNAPTIC MULTIPLICATION;

CMOS INTEGRATED CIRCUITS;

EID: 0036957023     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. C. Rasche and R. Douglas, "Forward- and backpropagation in a silicon dendrite," IEEE Trans. Neural Networks, vol. 12, no. 2, pp. 386-393, March 2001.
2. C. Diorio, D. Hsu, and M. Figueroa, "Adaptive CMOS: From biological inspiration to systems-on-a-chip," Proceedings of the IEEE, vol. 90, no. 3, pp. 345-357, March 2002.
3. J. Johnson and M. Padgett "PCNN models and applications," IEEE Trans. Neural Networks, vol. 10, no. 3, pp 480-498, May 1999.
4. L. Reyneri, "Theoretical and implementation aspects of pulse streams: an overview," in Proc. 7th Intl. Conf. Microelectronics for Neural, Fuzzy and Bio-Inspired Sys. (MicroNeuro '99), October 1999, pp. 78-89.
5. A. Murray, D. Del Corso, and L. Tarassenko, "Pulsed-stream VLSI neural networks mixing analog and digital techniques," IEEE Trans. Neural Networks, vol. 2, no. 2, pp. 193-204, March 1991.
6. Y. Ota and B. Wilamowski, "Analog implementation of pulsed-coupled neural networks," IEEE Trans. Neural Networks, vol. 10, no. 3, pp. 539-544, May 1999.
7. Y. Ota and B. Wilamowski, "CMOS architecture of synchronous pulse-coupled neural networks and its application to image processing," in Proc. 26th Annual Conf. IEEE Indus. Electron. Soc. (IECON'00), October 2000, pp. 1213-1218.
8. L. Chen and B. Shi, "CMOS PWM VLSI implementation of neural network," in Proc. IEEE-INNS-ENNS Intl. Conf. Neural Networks (IJCNN 2000), 2000, vol. 3, p. 485-488.
9. Y. Park, J.-S. Liaw, B. Sheu, and T. Berger, "Compact VLSI neural network circuit with high-capacity dynamic synapses," in Proc. IEEE-INNS-ENNS Intl. Conf. Neural Networks (IJCNN 2000), 2000, vol. 4, pp. 214-218.
10. H. Hikawa, "Pulse mode multilayer neural network based on floating point number representation," in Proc. IEEE Intl. Sym. Circuits and Systems (ISCAS 2000), 2000, vol. 3, pp. 145-148.
11. Y. Maeda and T. Tada, "FPGA implementation of a pulse density neural network using simultaneous perturbation," in Proc. IEEE-INNS-ENNS Intl. Conf. Neural Networks (IJCNN 2000), 2000, vol. 3, pp. 296-301.