Pulse mode multilayer neural network based on floating point number representation

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Hikawa, Hiroomi ^a  

^a OITA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; FIELD PROGRAMMABLE GATE ARRAYS;

FLOATING POINT NUMBER SYSTEMS;

MULTILAYER NEURAL NETWORKS;

EID: 0033699242     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856017     Document Type: Conference Paper

References (4)