Cool-mem: Combining statically speculative memory accessing with selective address translation for energy efficiency

International Conference on Architectural Support for Programming Languages and Operating Systems - ASPLOS

Volumn , Issue , 2002, Pages 133-143

  Ashok, Raksit ^a   Chheda, Saurabh ^a   Moritz, Csaba Andras ^a  

^a University of Massachusetts at Amherst   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER PERIPHERAL EQUIPMENT; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY UTILIZATION; EVALUATION; PERFORMANCE; POWER CONTROL; PROGRAM COMPILERS; ARCHITECTURE; ASSOCIATIVE STORAGE; COMPUTER OPERATING SYSTEMS; EMBEDDED SYSTEMS; ENERGY CONSERVATION; ENERGY EFFICIENCY; LINGUISTICS; TRANSLATION (LANGUAGES);

ADDRESS TRANSLATION; MEMORY SYSTEM;

ASSOCIATIVE STORAGE; PROGRAM COMPILERS;

ADDRESS TRANSLATION; ARCHITECTURAL ORGANIZATION; ASSOCIATIVE CACHE; CACHE ACCESS; COMPILER ANALYSIS; COMPLEX APPLICATIONS; COMPLEXITY ISSUES; CONVENTIONAL MEMORIES; ENERGY AWARE; ENERGY CONSUMPTION; GENERAL PURPOSE ARCHITECTURES; MEDIABENCH APPLICATIONS; MEMORY SYSTEMS; MULTI-LEVEL; POWER CONSUMED; PROVABLE CORRECTNESS; STATIC INFORMATION; TOTAL ENERGY; VIRTUAL MEMORY;

EID: 0036954638     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (32)

1. D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Proceedings of the 27th International Symposium on Computer Architecture (ISCA '00), June 2000.
2. D. C. Burger and T. M. Austin. The SimpleScalar Tool Set, Version 2.0. Technical Report CS-TR-1997-1342, 1997.
3. J. S. Chase, H. M. Levy, E. D. Lazowska, and M. Baker-Harvey. Lightweight Shared Objects in a 64-bit Operating System. Technical Report 92-03-09, University of Washington, March 1992.
4. J. B. Chen, A. Borg, and N. P. Jouppi. A Simulation-based Study of TLB Performance. In Proceedings of the 19th International Symposium on Computer Architecture (ISCA '92), May 1992.
5. R. Cheng. Virtual Address Cache in Unix. In Proceedings of the 1987 Summer Usenix Conference, pages 217-224, 1987.
6. C. Corporation. Alpha 21164 Microprocessor: Hardware Reference Manual. Digital Semiconductor, April 1995.
7. J. Cortadella and J. M. Llaberia. Evaluation of A+B=T condition without carry propogation. IEEE Transactions on Computers, November 1992.
8. J. R. Goodman. Coherency for Multiprocessor Virtual Address Caches. In Proceedings of the 2nd International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS '87), October 1987.
9. M. K. Gowan, L. L. Biro, and D. B. Jackson. Power Considerations in the Design of the Alpha 21264 Microprocessor. In Proceedings of the 35th Design Automation Conference (DAC '98), 1998.
10. M. Huang, J. Renau, S.-M. Yoo, and J. Torrellas. L1 Data Cache Decomposition for Energy Efficiency. In Proceedings of the International Symposium on Low-Power Electronics and Design (ISPLED '01), August 2001.
11. K. Inoue, T. Ishihara, and K. Murakami. Way-Predicting Set-Associative Cache for High Performance and Low Energy Consumption. In Proceedings of the International Symposium on Low-Power Electronic Design (ISPLED '99), August 1999.
12. A. Iyer and D. Marculescu. Power Aware Microarchitecture Resource Scaling. In Proceedings of the IEEE Design, Automation and Test in Europe (DATE), March 2001.
13. B. L. Jacob and T. N. Mudge. Software-Managed Address Translation. In Proceedings of the 3rd International Symposium on High Performance Computer Architecture (HPCA '97), February 1997.
14. B. L. Jacob and T. N. Mudge. Uniprocessor Virtual Memory without TLBs. In IEEE Transactions on Computers. IEEE Press, May 2001.
15. T. Juan, T. Lang, and J. J. Navarro. Reducing TLB power Requirements. In Proceedings of the International Symposium on Low Power Electronics and Design (ISPLED '97), August 1997.
16. J. Kin, M. Gupta, and W. M. Smith. The Filter Cache: An Energy Efficient Memory structure. In Proceedings of the 30th Annual Symposium on Microarchitecture (MICRO '97). IEEE Press, December 1997.
17. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communication Systems. In Proceedings of the 30th Annual Symposium on Microarchitecture (MICRO '97). IEEE Press, 1997.
18. A. Ma, M. Zhang, and K. Asanovic. Way Memoization to Reduce Fetch Energy in Instruction Caches. In Workshop on Complexity Effective Design, 28th International Symposium on Computer Architecture (ISCA '01), July 2001.
19. J. Montanaro. A 160-MHz, 32-b, 0.5-W CMOS RISC Microprocessor. In Digital Technical Journal, vol. 9, Digital Equipment Corporation, 1997.
20. C. A. Moritz, M. Frank, and S. Amarasinghe. FlexCache: A Framework for Compiler Generated Data Caching. In Lecture Notes in Computer Science. Springer Verlag, 2001.
21. C. A. Moritz, M. Frank, W. Lee, and S. Amarasinghe. Hot Pages: Software Caching for Raw Microprocessors. In MIT-LCS Technical Memo LCS-TM-599, Aug 1999.
22. D. A. Patterson and J. L. Hennessy. Computer Architecture: A Quantitative Approach. Morgan Kaufmann, San Mateo, CA, 1990.
23. M. D. Powell, A. Agarwal, T. N. Vijaykumar, B. Falsafi, and K. Roy. Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping. In 34th Annual Symposium on Microarchitecture (MICRO '01). IEEE Press, December 2001 (To Appear).
24. G. Reinman and N. Jouppi. An Integrated Cache Timing and Power Model. Compaq WRL Report, 1999.
25. S. Sair and M. Charney. Memory Behaviour of the SPEC2000 Benchmark Suite. IBM T. J. Watson Research Center Technical Report, 2000.
26. A. J. Smith. Cache Memories. In Computing Surveys, 14(3), pages 473-530, September 1982.
27. The standard performance evaluation corporation. In http://www.spec.org, 2000.
28. O. S. Unsal, R. Ashok, I. Koren, C. M. Krishna, and C. A. Moritz. Cool-Cache for Hot Multimedia. In 34th Annual Symposium on Microarchitecture (MICRO '01). IEEE Press, December 2001 (To Appear).
29. W.-H. Wang, J.-L. Baer, and H. M. Levy. Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. In Proceedings of the 16th International Symposium on Computer Architecture (ISCA '89), June 1989.
30. E. Witchel, S. Larsen, C. S. Ananian, and K. Asanovic. Direct Addressed Caches for Reduced Power Consumption. In 34th Annual Symposium on Microarchitecture (MICRO '01). IEEE Press, December 2001 (To Appear).
31. D. A. Wood, S. J. Eggers, G. Gibson, M. D. Hill, J. M. Pendleton, S. A. Ritchie, G. S. Taylor, R. H. Katz, and D. A. Patterson. An In-Cache Address Translation Mechanism. In Proceedings of the 13th International Symposium on Computer Architecture (ISCA '86), January 1986.
32. M. Zhang and K. Asanovic. Highly-Associative Caches for Low-Power Processors. In Kool Chips Workshop, 33rd Annual Symposium on Microarchitecture (MICRO '00), December 2000.