Reducing access energy of on-chip data memory considering active data bitwidth

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 88-91

  Okuma, Takanori ^a   Cao, Yun ^a   Muroyama, Masanori ^a   Yasuura, Hiroto ^a  

^a KYUSHU UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; ELECTRIC POWER SUPPLIES TO APPARATUS; MICROPROCESSOR CHIPS; MONOLITHIC INTEGRATED CIRCUITS;

DATA BITWIDTH; MONOLITHIC MEMORY; ON CHIP DATA MEMORY;

POWER ELECTRONICS;

EID: 0036954282     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.2002.146717     Document Type: Conference Paper

References (15)

1. L. Benini, A. Macii, E. Macii, and M. Poncino. "Synthesis of Application-Specific Memories for Power Optimization in Embedded Systems". In Proc. of 37th DAC, pages 300-303, June 2000.
2. L. Benini, A. Macii, and M. Poncino. "A Recursive Algorithm for Low-Power Memory Partitioning". In Proc. of International Symposium on Low Power Electronics and Design, pages 78-83, August 2000.
3. F. Catthoor, S. Wuytack, E.D. Greef, and F. Balasa. Custom Memory Management Methodology: Exploration of Memory Organization for Embedded Multimedia System Design. Kluwer, 1998.
4. S. L. Coumeri and D. E. Thomas. "An Environment for Exploring Low Power Memory Configurations in System Level Design". In Proc. of ICCDesign, pages 348-353, September 1999.
5. A. H. Farrahi, G. E. Tellez, and M. Sarrafzadeh. "Memory Segmentation to Exploit Sleep Mode Operation". In Proc. of 32th Design Automation Conference, pages 36-41, June 1995.
6. J. Hennessy and D. Patterson. Computer Architecture A Quantitive Approach. Morgan Kaufman, 1996.
7. T. Ishihara and H. Yasuura. "A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors". In Proc. of DATE, pages 617-622, March 2000.
8. U. Ko and P. Balsara. "Energy Optimization of Multilevel Cache Architectures for RISC and CISC Processors". IEEE Transactions on VLSI Systems, 6(2):pages 299-308, Jun 1998.
9. P. R. Panda, F. Catthoor, N. D. Dutt, K. Danckaert, E. Brockmeyer, and A. Vandercappelle. "Data and Memory Optimization Techniques for Embedded Systems". ACM Transactions of Design Automation of Electronics Systems, 6(2):pages 149-206, April 2001.
10. P.R. Panda and N.D. Dutt. "Low-Power Memory Mapping Through Reducing Address Bus Activity", IEEE Transactions on VLSI Systems, 7(3):pages 309-320, September 1999.
11. P. R. Panda, N. D. Dutt, and A. Nicolau. "On-Chip vs. Off-Chip Memory: The Data Partitioning Problem in Embedded Processor-Based Systems". ACM Transactions of Design Automation of Electronics Systems, 5(3):pages 682-704, July 2000.
12. J. Rabaey and M. Pedram. Low Power Design Methodologies. Kluwer, 1996.
13. W.-T. Shiue and C. Chakrabarti. "Memory Exploration for Low Power Embedded Systems". In Proc. of 36th Design Automation Conference, pages 140-145, June 1999.
14. C. Su and A. Despain. "Cache Design Tradeoffs for Power and Performance Optimization: A Case Study". In Proc. of International Symposium on Low Power Electronics and Design, pages 63-68, April 1995.
15. L. Villa, M. Zhang, and K. Asanovic. "Dynamic Zero Compression for Cache Energy Reduction". In Proc. of MICRO-33, 2000.