An assembly-level execution-time model for pipelined architectures

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 195-200

  Beltrame, G ^b   Brandolese, C ^a   Fornaciari, W ^a   Salice, F ^a   Sciuto, D ^a   Trianni, V ^a  

^a POLITECNICO DI MILANO   (Italy)

^b CEFRIEL   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTER SOFTWARE; ENERGY UTILIZATION; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PROGRAM ASSEMBLERS;

MICROPROCESSOR INSTRUCTION SETS;

PIPELINE PROCESSING SYSTEMS;

EID: 0035215348     PISSN: 10923152     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCAD.2001.968618     Document Type: Article

References (8)

1. Power analysis of embedded software: A first step towards software power minimization
2. Power analysis of the intel 486DX2
3. Software power estimation and optimization for high performance, 32-bit embedded processors
4. An instruction-level functionality-based energy estimation model for 32-bits microprocessors
5. Instruction level power model and its application to general purpose processors